1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. More particularly, example embodiments of the present invention relate to a semiconductor device having enhanced characteristics through compensating edge portions of an insulation layer and a method of manufacturing the same.
2. Description of the Related Art
Semiconductor devices are generally divided into volatile semiconductor memory devices and nonvolatile semiconductor memory devices. The volatile semiconductor memory devices such as dynamic random-access memory (DRAM) devices or static random-access memory (SRAM) devices lose data stored therein when power is turned off, and thus have some limitations in use. However, the nonvolatile semiconductor memory devices can maintain data stored therein even after power is turned off. Thus, the nonvolatile semiconductor memory devices such as a flash memory device have been greatly in demand. The flash memory device is electrically erasable and programmable.
The flash memory device includes a memory cell for storing data that has a stacked gate structure. In particular, the memory cell includes a tunnel oxide layer formed on a semiconductor substrate including an isolation layer, a floating gate formed on the tunnel oxide layer, a dielectric layer formed on the floating gate, and a control gate formed on the dielectric layer. The flash memory device stores data by controlling the number of electrons placed on the floating gate of the memory cell. The number of electrons on the floating gate is varied by properly applying power to the control gate and the semiconductor substrate. The dielectric layer serves to maintain the electrons accumulated in the floating gate, and to convey power applied to the control gate to the floating gate.
In a method of manufacturing a conventional nonvolatile memory device, a tunnel oxide layer and a floating gate are successively formed on a semiconductor substrate on which an isolation layer is formed. The tunnel oxide layer and the floating gate are formed on an active region of the semiconductor substrate by a photolithography process. In the photolithography process, the floating gate and the active region may be misaligned. As a line width of the nonvolatile memory device is reduced, there are limitations in ensuring an alignment error margin between the floating gate and the active region.
To solve the above problems, a new method of manufacturing the nonvolatile memory device has been developed as disclosed in Korean Laid-Open Patent Publication No. 2005-30008. In the method, a floating gate of the nonvolatile memory device is formed by a self-alignment process, in which the floating gate is self-aligned relative to isolation regions having protruded upper portions. Particularly, a mask pattern having a predetermined thickness is formed on a semiconductor substrate. Trenches are formed on the semiconductor substrate using the mask pattern. The trenches are filled with an insulation material up to an upper face of the mask pattern. As a result, isolation regions having protruded upper portions are formed on the semiconductor substrate to define an active region and a field region in the semiconductor substrate. The mask pattern is removed from the semiconductor substrate to form an opening that exposes the active region of the semiconductor substrate between the isolation regions. A tunnel oxide layer is formed on a bottom of the opening. The floating gate is formed on the tunnel oxide layer to fill up the opening.
In a process of removing the mask pattern, the protruded upper portions of the isolation regions are partially etched so that the opening has a width substantially wider than that of the active region. Thus, the tunnel oxide layer and the floating gate have widths substantially wider than that of the active region. The tunnel oxide layer is also formed on edge portions of the active region. The edge portions of the active region are affected by concentrated stress so that the tunnel oxide formed on the edge portions of the active region has a thickness substantially thinner than that of the tunnel oxide layer formed on a center portion of the active region. When the tunnel oxide layer has a partially thin portion, a Fowler-Nordheim (F-N) tunneling through the tunnel oxide layer is concentrated on the thin portion of the tunnel oxide layer. Thus, electrical characteristics of the nonvolatile memory device are deteriorated. Furthermore, the electrons on the floating gate easily leak through the thin portion of the tunnel oxide layer. Therefore, reliability of the nonvolatile memory device is also reduced.
To prevent thinning of a tunnel oxide layer and to form the tunnel oxide layer having a uniform thickness, some methods have been developed. Korean Patent No. 466,195 discloses a method of prevent thinning of the tunnel oxide layer by controlling an edge profile of a trench for forming an isolation layer on a semiconductor substrate. The trench of which edge portion has a double profile is formed by properly etching a mask pattern formed on the semiconductor substrate and the semiconductor substrate, and by forming a sacrificial oxide layer on a sidewall of the trench. As a result, generation of a moat on an edge portion of the tunnel oxide layer and thinning of the tunnel oxide layer are prevented. Korean Patent No. 466,189 discloses a method of preventing thinning of the tunnel oxide layer by rounding an edge portion of a trench for forming an isolation layer at a semiconductor substrate. The edge portion of the trench is rounded by an annealing process under a hydrogen atmosphere. In the above methods, thinning of the tunnel oxide layer is prevented by improving a structure of a trench for forming an isolation layer.
Korean Patent No. 284,140 discloses a re-oxidation process for thickening edge portions of a tunnel oxide layer and a floating gate after a formation of a gate structure including the tunnel oxide layer, the floating gate, a dielectric layer and a control gate on a semiconductor substrate. In the method, the dielectric layer and the control gate are also oxidized in the re-oxidation process. For example, when the control gate is formed by using a metal such as tungsten, the control gate is oxidized in the re-oxidation process so that electrical characteristics of the control gate are greatly deteriorated.
Japanese Laid-Open Patent Publication No. 11-17033 discloses a method of forming a flash memory device. In the method, an isolation layer is formed on a semiconductor substrate, and then a tunnel oxide layer is formed on the semiconductor substrate. A polysilicon layer that serves as a floating gate is formed on the tunnel oxide layer. After impurities are implanted into the polysilicon layer by an ion implantation process, the polysilicon layer is oxidized to form an oxide layer on the polysilicon layer. The oxidation process just serves to control a thickness of the polysilicon layer and to form the polysilicon having a uniform thickness, not to prevent thinning of the tunnel oxide layer.